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ADS5463IPFPR Datasheet(PDF) 6 Page - Texas Instruments |
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ADS5463IPFPR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 37 page  N CLK D OVR [11:0], N+1 N+5 t CLKL t DRY t DATA t CLKH t a D[11:0], OVR CLK N+2 N+3 N+4 DRY DRY (1) N N+1 N–1 Sample N–1 Latency = 3.5 Clock Cycles TIMING CHARACTERISTICS (1) ADS5463 SLAS515B – NOVEMBER 2006 – REVISED MAY 2008 .................................................................................................................................................... www.ti.com (1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section. Figure 1. Timing Diagram Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 200 ps Aperture jitter, rms 150 fs Latency 3.5 cycles tCLK Clock period 2 50 ns tCLKH Clock pulse duration, high 1 ns tCLKL Clock pulse duration, low 1 ns Zero crossing, 10-pF parasitic loading to GND on each tDRY CLK to DRY delay(2) 950 1600 ps output pin Zero crossing, 10-pF parasitic loading to GND on each tDATA CLK to DATA/OVR delay(2) 750 2100 ps output pin tDATA – tDRY, 10-pF parasitic loading to GND on each output tSKEW DATA to DRY skew –350 0 650 ps pin tRISE DRY/DATA/OVR rise time 10-pF parasitic loading to GND on each output pin 500 ps tFALL DRY/DATA/OVR fall time 10-pF parasitic loading to GND on each output pin 500 ps (1) Timing parameters are specified by design or characterization, but not production tested. (2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay. 6 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s) :ADS5463 |
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