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ADS5463IPFPRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5463IPFPRG4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 37 page  ADS5463 SLAS515B – NOVEMBER 2006 – REVISED MAY 2008 .................................................................................................................................................... www.ti.com Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. AIN 16 Differential input signal (positive) AIN 17 Differential input signal (negative) 3, 8, 13, 14, 19, 21, AVDD5 Analog power supply (5 V) 23, 25, 27, 31 Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for AVDD3 35, 37, 39 ADS5440/4 13-bit compatibility) DVDD3 1, 51, 66 Output driver power supply (3.3 V) 2, 7, 9, 12, 15, 18, 20, 22, 24, 26, 28, GND Ground 30, 32, 34, 36, 38, 40, 52, 65 CLK 10 Differential input clock (positive). Conversion is initiated on rising edge. CLK 11 Differential input clock (negative) D0, D0 54, 53 LVDS digital output pair, least-significant bit (LSB) D1–D10, 55–64, LVDS digital output pairs D1–D10 67–76 D11, D11 78, 77 LVDS digital output pair, most-significant bit (MSB) DRY, DRY 80, 79 Data ready LVDS output pair No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout NC 4, 5, 43–50 and therefore can be connected to a digital bus or left floating) Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale OVR, OVR 42, 41 range. Pin 29 is reserved for possible future Vcm output for this pinout, like ADS5474; pin 33 is reserved for RESERVED 29, 33 possible future power-down control pin for this pinout, like ADS5474. VREF 6 Reference voltage input/output (2.4V nominal) 8 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s) :ADS5463 |
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