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XC2286-XXF66L Datasheet(PDF) 7 Page - Infineon Technologies AG |
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XC2286-XXF66L Datasheet(HTML) 7 Page - Infineon Technologies AG |
7 / 647 page User’s Manual L-3 V1.0, 2007-06 XC2000 Derivatives System Units (Vol. 1 of 2) Table Of Contents Preliminary Summary Of Chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-1 [1] Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-3 [1] 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1] 1.1 Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1] 1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1] 1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1] 1.4 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1] 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1] 2.1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1] 2.1.1 High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1] 2.1.2 Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1] 2.1.3 High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1] 2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1] 2.1.5 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1] 2.1.6 Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1] 2.2 On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1] 2.3 On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 [1] 2.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1] 2.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 [1] 2.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 [1] 3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1] 3.1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1] 3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1] 3.3 Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 [1] 3.4 Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 [1] 3.4.1 Program/Data SRAM (PSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1] 3.4.2 Non-Volatile Program Memory (Flash) . . . . . . . . . . . . . . . . . . . . . 3-13 [1] 3.5 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1] 3.6 IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1] 3.7 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1] 3.8 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 [1] 3.9 Embedded Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] 3.9.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] Table Of Contents This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For your convenience this table of contents (and also the keyword and register index) lists both volumes, so you can immediately find the reference to the desired section in the corresponding document ([1] or [2]). |
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