MC54/74HC165A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Unit

Guaranteed Limit

VCC

V

Test Conditions

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

VOL

Maximum Low–Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

2.0

3.0

4.5

6.0

10

15

30

50

9

14

28

45

8

12

25

40

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH

(Figures 1 and 8)

2.0

3.0

4.5

6.0

110

36

22

19

125

45

26

23

160

60

32

28

ns

tPLH,

tPHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH

(Figures 2 and 8)

2.0

3.0

4.5

6.0

85

57

25

19

96

63

29

23

106

71

32

27

ns

tPLH,

tPHL

Maximum Propagation Delay, Input H to QH or QH

(Figures 3 and 8)

2.0

3.0

4.5

6.0

110

36

22

19

125

45

26

23

160

60

32

28

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

16

110

36

22

19

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Package)*

40

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).