Electrical specifications

L6452

10/22

Theoretical acquisition time

32.4

µs

Real acquisition time

36

µs

DIGITAL INTERFACE INPUT

Schmitt Trigger positive-going

Threshold

V

Schmitt Trigger negative-going

Threshold

V

Schmitt Trigger Hysteresis

0.1

0.3

1

V

(4)

50

150

300

µA

CR LATCH TIMINGS

Latch set up time

100

ns

Latch high time

100

ns

Latch data valid to A/D input

valid delay

Selected channel:

CH1..CH5

CH0

4

7

µs

µs

Latching data time

200

ns

Note:

The control register (driving signals CRdata, CRclock) is accessed with the same timing

specifications as the data 16 bit shift register (signals SDI, SDC)

SHIFT REGISTER AND LATCH TIMING

Set up time

35

ns

Hold time

35

ns

Serial clock low time

35

ns

Serial clock high time

35

ns

Serial clock period

125

ns

Latch set up time

100

ns

Latch data high time

100

ns

NcEn setup time with respect

to LongPulse (or ShortPulse)

Asserted

160

ns

NcEn hold time with respect to

LongPulse (or ShortPulse)

Asserted

0ns

Set-up time from latch to Pulse

(short and long)

125

ns

Time from Pulse deassertion to

new data latching

125

ns

Table 3.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit