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HC6856XQFCC35 Datasheet(PDF) 2 Page - Honeywell Solid State Electronics Center

Part # HC6856XQFCC35
Description  32K x 8 STATIC RAM
Download  12 Pages
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Manufacturer  HONEYWELL [Honeywell Solid State Electronics Center]
Direct Link  http://honeywell.com/Pages/Home.aspx
Logo HONEYWELL - Honeywell Solid State Electronics Center

HC6856XQFCC35 Datasheet(HTML) 2 Page - Honeywell Solid State Electronics Center

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HC6856
2
FUNCTIONAL DIAGRAM
NCS
CE
NWE
NOE
MODE
DQ
L
H
H
L
Read
Data Out
L
H
L
X
Write
Data In
H
X
XX
XX
Deselected
High Z
X
L
XX
XX
Disabled
High Z
TRUTH TABLE
NCS
A:0-8,12-13
CE
NWE
NOE
CS • CE
WE • CS • CE
NWE • CS • CE • OE
Column Decoder
Data Input/Output
Row
Decoder
32,768 x 8
Memory
Array
A:9-11,14
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
1 = enabled
Signal
4
DQ:0-7
(0 = high Z)
8
8
11
SIGNAL DEFINITIONS
A: 0-14
Address input pins (A) which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces
the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all
the input buffers. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level it allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers.
If this signal is not used it must be connected to VDD.
Notes:
X: VI=VIH or VIL
XX: VSS
≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X


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