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STLC5460 Datasheet(PDF) 4 Page - STMicroelectronics |
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STLC5460 Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 54 page PIN DEFINITIONS AND FUNCTIONS (continued) Symbol Pin n PLCC Type Function AS/ALE 31 I Multiplexed A/D mode: used to latch the address from ADn Non Multiplexed A/D Mode: This pin at VSS indicates Intel like interfaces This pin at VDD indicates Motorola like interfaces. INT 32 OD Interrupt line, active low. DCL 33 0 Data clock output. FSC 34 O Frame synchronization output. VDD2 35 I Power supply : 5V VSS2 36 I Ground. DIN1 37 I GCI Data input 1 DIN0 38 I GCI Data input 0 A3 39 I (**) Non Multiplexed Mode: this input interfaces to the system’s address bus to select an internal register for a read or write access. Multiplexed Mode: A3 at VDD, DS/NRD signal provided by the system is not inverted by the circuit A3 at VSS, DS/NRD signal provided by the system isinverted by the circuit DOUT0 40 O GCI Data Output 0 DOUT1 41 O GCI Data Output 1 PO 42 I (**) P0 at VSS: variable access mode P0 at VDD: fixed access mode NRDY/N WAIT 43 OD If P0 at VSS: Intel like mode: this pin delivers NRDY Motorola mode: this pin delivers NWAIT RES 44 I Reset. A logical high on this input forces the STLC5460 into the reset state (*): (I) Input (O) Output (IO) In/Output (OD) Open Drain (**): With Pull up resistance. DCL FSC DOUT0 DIN0 DOUT1 DIN1 MUX0/GCI0 MUX1/GCI1 LCIC PCM3 PCM0 PCM1 PCM2 PDC PFS RxD3 TxD3 TSC3 RxD0 TxD0 TSC0 RxD1 TxD1 TSC1 RxD2 TxD2 TSC2 MICROPROCESSOR INTERFACE D94TL159A CLOCKS Figure 1: GCI and PCM Interfaces. STLC5460 4/54 |
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