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74LVQ273 Datasheet(PDF) 2 Page - STMicroelectronics |
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74LVQ273 Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 13 page 74LVQ273 2/13 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description Table 3: Truth Table X : Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays PIN No SYMBOL NAME AND FUNCTION 1CLEAR Asynchronous Master Reset (Active LOW) 2, 5, 6, 9, 12, 15, 16,19 Q0 to Q7 Flip-Flop Outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 11 CLOCK Clock Input (LOW-to-HIGH Edge Triggered) 10 GND Ground (0V) 20 VCC Positive Supply Voltage INPUTS OUTPUT FUNCTION CLEAR DCLOCK Q L X X L CLEAR HL L HH H HX Qn NO CHANGE |
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