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74VHC273 Datasheet(PDF) 1 Page - STMicroelectronics |
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74VHC273 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 14 page  1/14 November 2004 s HIGH SPEED: fMAX = 165 MHz (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.9V (MAX.) DESCRIPTION The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74VHC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74VHC273MTR TSSOP 74VHC273TTR TSSOP SOP Rev. 5 |
Similar Part No. - 74VHC273_04 |
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Similar Description - 74VHC273_04 |
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