74VHC574

2/14

Figure 2: Input Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Z : High Impedance

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

PIN N°

SYMBOL

NAME AND FUNCTION

1OE

3-State Output Enable

Input (Active LOW)

2, 3, 4, 5, 6,

7, 8, 9

D0 to D7

Data Inputs

12, 13, 14,

15, 16, 17,

18, 19

Q0 to Q7

3-State Outputs

11

CK

Clock Input (LOW-to-HIGH

Edge Triggered)

10

GND

Ground (0V)

20

Positive Supply Voltage

INPUTS

OUTPUT

OE

CK

D

Q

HX

X

Z

L

X

NO CHANGE

LL

L

LH

H