6.1.3
Power Control ........................................................................................................................... 57
6.1.4
Clock Control ............................................................................................................................ 57
6.1.5
System Control ......................................................................................................................... 59
6.2
Initialization and Configuration ................................................................................................... 60
6.3
Register Map ............................................................................................................................ 60
6.4
Register Descriptions ................................................................................................................ 61
7
Hibernation Module .......................................................................................................... 112
7.1
Block Diagram ........................................................................................................................ 113
7.2
Functional Description ............................................................................................................. 113
7.2.1
Register Access Timing ........................................................................................................... 113
7.2.2
Clock Source .......................................................................................................................... 114
7.2.3
Battery Management ............................................................................................................... 114
7.2.4
Real-Time Clock ...................................................................................................................... 114
7.2.5
Non-Volatile Memory ............................................................................................................... 115
7.2.6
Power Control ......................................................................................................................... 115
7.2.7
Interrupts and Status ............................................................................................................... 115
7.3
Initialization and Configuration ................................................................................................. 116
7.3.1
Initialization ............................................................................................................................. 116
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 116
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 116
7.3.4
External Wake-Up from Hibernation .......................................................................................... 117
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 117
7.4
Register Map .......................................................................................................................... 117
7.5
Register Descriptions .............................................................................................................. 118
8
Internal Memory ............................................................................................................... 131
8.1
Block Diagram ........................................................................................................................ 131
8.2
Functional Description ............................................................................................................. 131
8.2.1
SRAM Memory ........................................................................................................................ 131
8.2.2
Flash Memory ......................................................................................................................... 132
8.3
Flash Memory Initialization and Configuration ........................................................................... 133
8.3.1
Flash Programming ................................................................................................................. 133
8.3.2
Nonvolatile Register Programming ........................................................................................... 134
8.4
Register Map .......................................................................................................................... 134
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 135
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 142
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 155
9.1
Functional Description ............................................................................................................. 155
9.1.1
Data Control ........................................................................................................................... 155
9.1.2
Interrupt Control ...................................................................................................................... 156
9.1.3
Mode Control .......................................................................................................................... 157
9.1.4
Commit Control ....................................................................................................................... 157
9.1.5
Pad Control ............................................................................................................................. 157
9.1.6
Identification ........................................................................................................................... 157
9.2
Initialization and Configuration ................................................................................................. 157
9.3
Register Map .......................................................................................................................... 159
9.4
Register Descriptions .............................................................................................................. 160
October 09, 2007
4
Preliminary
Table of Contents