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V62C2801024L-70T Datasheet(PDF) 1 Page - Mosel Vitelic, Corp

Part # V62C2801024L-70T
Description  Ultra Low Power 128K x 8 CMOS SRAM
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Manufacturer  MOSEL [Mosel Vitelic, Corp]
Direct Link  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V62C2801024L-70T Datasheet(HTML) 1 Page - Mosel Vitelic, Corp

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7
8
9
16
15
14
13
12
11
10
A8
A9
A11
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
17
18
19
20
21
22
23
CE1
A10
OE
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1024
X
1024
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O7
I/O0
OE
WE
CE1
CE2
A9
A10
A11
A12
A13
A14
A15
A16
A8
A7
A6
A5
A4
A3
A2
A1
A0
V62C2801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 5
µA (CMOS input/output)
1
µA CMOS input/output, L version
• Single +2.2V to 2.7V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Functional Description
TheV62C2801024L is a low power CMOS Static RAM org-
anized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW CE1 , an active HIGH CE2, an
active LOW OE, and Tri-state I/O’s. This device has an a-
utomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1) with Output Enable
(OE) LOW while Write Enable (WE) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are d-
isabled during a write cycle.
TheV62C2801024LL comes with a 1V data retention feature
and Lower Standby Power. The V62C2801024L is available in
a 32pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
32-Pin TSOP1 / STSOP / 48-fpBGA (See nest page)
Logic Block Diagram
1024
X
1024
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
I/O8
I/O1
OE
WE
CE1
CE2
A10
A11
A12
A13
A14
A15
A16
A8
A7
A6
A5
A4
A3
A2
A1
A0
A9
REV. 1.1 April 2001 V62C2801024L(L)
1


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