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STM8AP6X66TAY Datasheet(PDF) 58 Page - STMicroelectronics |
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STM8AP6X66TAY Datasheet(HTML) 58 Page - STMicroelectronics |
58 / 100 page Electrical characteristics STM8AF61xx, STM8AF51xx 58/100 11.3.1 Supply current characteristics The current consumption is measured as described in Figure 8 on page 54 and Figure 9 on page 55. Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Note on the run-current typical and worst-case values ● Typical device currents values are representative of an application set-up without any I/O activity at 25 °C. The worst case values correspond to the actual test-limits and include both internal and external device I/O current. ● During the execution of an actual application program, the number of read access cycles to the code memory depends on its structure. A code doing arithmetical calculations reads the memory less frequently than programs with jump, loop or data manipulation instructions. The fast-reading access in a Flash memory needs much more power compared to a RAM. Consequently, the run-current for EEPROM execution depends strongly on the actual application code structure. The measurements in the tables below were made using a short, representative code with move, jump and arithmetic operations. The worst case, an infinite loop of ‘while’ instructions takes approximately 25 % more power. For RAM execution, such power to program structure relations has not been observed. Table 18. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate 20(1) 1. Guaranteed by design, not tested in production ∞ µs/V VDD fall time rate (3) 20(2) 2. TBD = To be determined ∞ tTEMP Reset release delay VDD rising TBD(2) 3ms Reset generation delay(3) 3. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed. VDD falling TBD(2) 3µs VIT+ Power-on reset threshold 2.65 2.8 2.95 V VIT- Brown-out reset threshold 2.58 2.73 2.88 V VHYS(BOR) Brown-out reset hysteresis 70(1) mV |
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