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ISPLSI2192VE Datasheet(PDF) 5 Page - Lattice Semiconductor

Part No. ISPLSI2192VE
Description  3.3V In-System Programmable SuperFASTâ„¢ High Density PLD
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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Specifications ispLSI 2192VE
5
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2192VE
1
3
2
1
tsu2 + tco1
(
)
DESCRIPTION
#
PARAMETER
A1
Data Propagation Delay, 4PT Bypass, ORP Bypass
ns
tpd2
A2
Data Propagation Delay
ns
fmax
A3
Clock Frequency with Internal Feedback
MHz
fmax (Ext.)
–4
Clock Frequency with External Feedback
MHz
fmax (Tog.)
–5
Clock Frequency, Max. Toggle
MHz
tsu1
–6
GLB Reg. Setup Time before Clock, 4 PT Bypass
ns
tco1
A7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
th1
–8
GLB Reg. Hold Time after Clock, 4 PT Bypass
ns
tsu2
–9
GLB Reg. Setup Time before Clock
ns
tco2
A10
GLB Reg. Clock to Output Delay
ns
th2
–11
GLB Reg. Hold Time after Clock
ns
tr1
A12
Ext. Reset Pin to Output Delay, ORP Bypass
ns
trw1
–13
Ext. Reset Pulse Duration
ns
tptoeen
B14
Input to Output Enable
ns
tptoedis
C15
Input to Output Disable
ns
tgoeen
B16
Global OE Output Enable
ns
tgoedis
C17
Global OE Output Disable
ns
twh
–18
External Synchronous Clock Pulse Duration, High
ns
twl
–19
External Synchronous Clock Pulse Duration, Low
ns
-180
MIN. MAX.
–
5.0
–
180
–
–
–
–
–
0.0
4.5
–
0.0
–
4.0
–
–
–
–
2.5
–
2.5
–
125
200
3.5
3.5
–
–
4.5
–
7.0
–
10.0
10.0
5.0
5.0
7.5
-225
MIN. MAX.
–
4.0
–
225
–
–
–
–
–
0.0
3.5
–
0.0
–
3.5
–
–
–
–
2.0
–
2.0
–
150
250
2.5
3.2
–
–
3.7
–
6.0
–
6.0
6.0
4.5
4.5
6.2




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