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ISPLSI3256E Datasheet(PDF) 1 Page - Lattice Semiconductor

Part No. ISPLSI3256E
Description  In-System Programmable High Density PLD
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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 1 page
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ispLSI® 3256E
In-System Programmable High Density PLD
3256e_09
1
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 100 MHz Maximum Operating Frequency
tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
C0
C1
C2
C3
ORP
ORP
Global Routing Pool
D0
D1
D2
D3
H3
H2
H1
H0
G3
G2
G1
G0
B0
B1
B2
B3
Boundary
Scan
OR
Array
DQ
DQ
DQ
DQ
Twin
GLB
OR
Array
DQ
DQ
DQ
DQ
A0
A1
A2
A3
E3
E2
E1
E0
F3
F2
F1
F0
0139A/3256E
ORP
ORP
ORP
ORP
ORP
ORP
Description
The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele-
ments.
The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
March 2007
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com




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