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ORLI10G Datasheet(PDF) 4 Page - Lattice Semiconductor |
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ORLI10G Datasheet(HTML) 4 Page - Lattice Semiconductor |
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4 / 80 page  Lattice Semiconductor ORCA ORLI10G Data Sheet 4 Programmable Logic System Features • PCI local bus compliant for FPGA I/Os. • Improved PowerPC ®/PowerQUICC 860, and PowerPC/PowerQUICC II MPC8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space is provided. • New embedded AMBA™ specification 2.0 AHB system bus (ARM ® processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. • Variable-size bused readback of configuration data capability with the built-in microprocessor interface and sys- tem bus. • Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. • New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E04). • New local clock routing structures allow creation of localized clock trees. • Two new edge clock structures allow up to six high speed clocks on each edge of the device for improved setup/hold and clock-to-out performance. • New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high- speed memory interfaces. • New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced-speed internal logic. • ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. • Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-PHY3. Also meets proposed specifications for UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces. • Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-over-SONET as defined by the Saturn Group. Features of the 10G PCS IP Core Programmable logic provides a variety of yet-to-be standardized interface functions, including the following IP core functions (IP Cores sold separately): • 10 Gbits/s Ethernet Physical Coding Sublayer (PCS), as defined by IEEE 802.3ae: – XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short-reach (typically less than 3 in.) interconnect interface. – Elastic store buffers for clock domain transfer to/from the XGMII interface. –X 59 + X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet. – 64b/66b encoders/decoders for 10 Gbits/s Ethernet. – Idle insertion and deletion. – SMI interface for control and status. • Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/SDH MUX/deMUX functions. |
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Similar Description - ORLI10G |
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