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OR4E02-3BM680C Datasheet(PDF) 4 Page - Lattice Semiconductor |
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OR4E02-3BM680C Datasheet(HTML) 4 Page - Lattice Semiconductor |
4 / 152 page 4 4 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs System Features ■ PCI local bus compliant. ■ Improved PowerPC ® /PowerQUICC MPC860 and PowerPC II MPC8260 high-speed synchronous microprocessor interface can be used for configura- tion, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC proces- sors with user-configurable address space provided. ■ New embedded AMBA ™ specification 2.0 AHB sys- tem bus (ARM ™ processor) facilitates communica- tion among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. ■ New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications. ■ Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. ■ Internal, 3-state, bidirectional buses with simple con- trol provided by the SLIC. ■ New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E04). ■ New local clock routing structures allow creation of localized clock trees. ■ Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. ■ New double-data rate (DDR) and zero-bus turn- around (ZBT) memory interfaces support the latest high-speed memory interfaces. ■ New 2x/4x uplink and downlink I/O capabilities inter- face high-speed external I/Os to reduced speed internal logic. ■ Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed specifications for UTOPIA level 4, POS- PHY Level 3 (2.5 Gbits/s), and POS-PHY 4 (10 Gbits/s) interface standards for packet-over-SONET as defined by the Saturn Group. ■ ispLEVER development system software. Supported by industry-standard CAE tools for design entry, syn- thesis, simulation, and timing analysis. |
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