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LA4032V-75TN128E Datasheet(PDF) 2 Page - Lattice Semiconductor

Part # LA4032V-75TN128E
Description  3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LA4032V-75TN128E Datasheet(HTML) 2 Page - Lattice Semiconductor

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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
2
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple
density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2
show the macrocell, package and I/O options, along with other key parameters.
The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V
and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA-
ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper
latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z
automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks
(GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O
Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
LA-ispMACH 4032Z
LA-ispMACH 4064Z
LA-ispMACH 4128Z
Macrocells
32
64
128
I/O + Dedicated Inputs
32+4
32+4/64+10
64+10
tPD (ns)
7.5
7.5
7.5
tS (ns)
4.5
4.5
4.5
tCO (ns)
4.5
4.5
4.5
fMAX (MHz)
168
168
168
Supply Voltage (V)
1.8V
1.8V
1.8V
Pins/Package
48-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
100-pin Lead-Free TQFP
I/O
Block
ORP
ORP
16
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP
ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O
Block
36
36
16
16
16
16
16


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