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ORSPI4-1FE1036I Datasheet(PDF) 10 Page - Lattice Semiconductor |
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ORSPI4-1FE1036I Datasheet(HTML) 10 Page - Lattice Semiconductor |
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10 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 10 SPI4 Transmit Path Overview The first of the major blocks in the Transmit section contains four DPRAM banks which can be configured to provide 32-bit, 64-bit or 128-bit data bus interfaces from the FPGA to the embedded core. Providing a scalable data bus enables users to tailor the transmit interface to meet their port bandwidth requirements. For example, with a POS- PHY Level 3 (PL3) interface supporting multiple PHYs (ports), a single 32-bit interface to the Transmit DPRAM is required. For an Ethernet 10 Gbits/s interface, a single port will require a single 128-bit interface to the Transmit DPRAM. To realize the various data bus interfaces or aggregation modes, the user must configure the mode within the embedded core via the MPI interface or the system bus. Multiple DPRAM banks can be aggregated into larger FIFOs. Division of the DPRAM banks into virtual partitions (up to eight) is also possible. The FPGA logic initiates a write to DPRAM by providing Data, Port ID, 3-bit FIFO Address and Write Enable signals to the SPI4 block. The internal FIFO controller latches the data and port control information into a temporary hold register that stores the data until an entire 128-bit line is captured, or an EOP is asserted. The 128-bit line is then written into the selected virtual FIFO. Associated with each FPGA data write interface, there are also control information signals and a transmit clock. The FIFO control logic transparently passes the control information to the Control memory, with the exception of the Byte Enable bits (BE[3:0]), which indicate which bytes of the associated 32-bit Word are valid. The DPRAM read logic blocks poll port data from the DPRAM banks, based on a preconfigured calendar sequence and the current status of each active port. The SPI4 calendar is a mechanism that maintains out-of-band statistics of the current status of each port supported across the SPI4 interface. The calendar is a reverse direction flow-con- trol mechanism used to control the dynamic bandwidth allocated for the each supported port. By periodically pro- viding far end receive status for each port, the transmitter can modulate the amount of bandwidth allocated to a particular port dynamically. Writes to the DPRAMs from the FPGA logic are asynchronous to the calendar polling algorithm. The SPI4 transmit logic reads data from the DPRAMs according to a strict calendar sequence algorithm and will generally not read port data from the virtual FIFOs in the sequence it was written. Both a main and a shadow calendar are provided and are each 1K deep. This enables the user to provide finer granularity of the polling sequence based on bandwidth allocated for each port. The length of the calendar table (CALENDAR_LEN) is programmable. CALENDAR_LEN should be at least as large as the number of active ports (channels) in the system and should not exceed the upper threshold set by the parameter (MAX_CALENDAR_LEN). There are two basic modes supported for transmitting data. Within the SPI4 core, the embedded core operates identically for all modes. At the FPGA interface, processing will be done slightly differently, depending upon the mode the user requires. Each mode is discussed below. • Embedded memory mode - This mode is used when the ORSPI4 is interfacing to asynchronous FPGA inter- faces, such as POS-PHY Level 3, 1GbE, Utopia Level 3, etc. and storing the data in the virtual DPRAM FIFOs. When operating in this mode, the SPI4 transmit logic will read port data from the FIFOs according to the calendar sequence. If there is no data, it will send idle data and advance to the next port. It is the user's responsibility to ensure the proper port data has been written to the virtual FIFO. • External memory mode - This mode is used in conjunction with the Memory Controller or some other external memory based interface where data is available only after some fixed delay. In this mode the SPI4 transmit logic instructs the FPGA as to what port data to retrieve as well as how many bursts of data to retrieve. The FPGA is responsible to write the data read from the Memory Controller into the DPRAMs. Data is read from the DPRAM devices by the SPI4 transmit logic according to the transmit calendar. The DPRAM read logic also includes a Port Descriptor Memory (PDM) which is a user configurable memory con- taining a list of read control parameters for all enabled ports to be polled. The depth of the memory is 256 locations, |
Similar Part No. - ORSPI4-1FE1036I |
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Similar Description - ORSPI4-1FE1036I |
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