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ORSO42G5-1BMN484I Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ORSO42G5-1BMN484I Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 153 page Lattice Semiconductor ORCA ORSO42G5 and ORSO82G5 Data Sheet 2 Table of Contents Introduction .................................................................. 1 Table of Contents......................................................... 2 Embedded Function Features...................................... 3 Programmable Features .............................................. 4 Programmable Logic System Features........................ 5 Description ................................................................... 6 What Is an FPSC? .......................................... 6 FPSC Overview............................................... 6 FPSC Gate Counting ...................................... 6 FPGA/Embedded Core Interface .................... 6 ispLEVER Development System..................... 7 FPSC Design Kit ............................................. 7 ORSO82G5/42G5 FPGA Logic Overview....... 7 ORCA Series 4 FPGA Logic Overview ........... 7 PLC Logic........................................................ 8 Programmable I/O........................................... 8 Routing............................................................ 9 System Level Features ................................... 9 MicroProcessor Interface ................................ 9 System Bus ..................................................... 9 Phase-Locked Loops ...................................... 9 Embedded Block RAM .................................. 10 Configuration................................................. 10 ORSO42G5 and ORSO82G5 Overview .................... 10 Embedded Core Overview ............................ 11 ORSO42G5 and ORSO82G5 Main Operating Modes - Overview .................. 12 Embedded Core Functional Blocks - Overview................................................. 13 Loopback - Overview .................................... 14 FPSC Configuration - Overview .................... 15 ORSO42G5 and ORSO82G5 Embedded Core Detailed Description ............................................ 16 Top Level Description - Transmitter (TX) and Receiver (RX) Architectures ............ 16 Detailed Description - SERDES Only Mode....................................................... 19 32:8 MUX ...................................................... 21 SONET Mode Operation – Detailed Description ............................... 24 SONET Mode Transmit Path ........................ 30 SONET Mode Receive Path ......................... 33 Cell Mode Detailed Description..................... 49 Cell Mode Transmit Path............................... 52 Cell Mode Receive Path................................ 56 Cell Extractor................................................. 56 Receive FIFO ................................................ 57 Input Port Controllers .................................... 57 IPC Receive Cell Mode Timing Core/FPGA ............................................. 59 Reference Clock Requirements .................... 67 Sample Initialization Sequences – ORSO42G5......... 69 Sample Initialization Sequences – ORSO82G5......... 70 Reset Conditions........................................................ 72 SERDES Characterization Test Mode (ORSO82G5 Only)............................................... 73 Embedded Core Block RAM ...................................... 74 Register Maps ............................................................ 76 Types of Registers ........................................ 77 Absolute Maximum Ratings ..................................... 108 Recommended Operating Conditions ...................... 108 SERDES Electrical and Timing Characteristics ....... 108 High Speed Data Transmitter...................... 109 High Speed Data Receiver.......................... 110 External Reference Clock ........................... 112 Pin Descriptions ....................................................... 113 Power Supplies ........................................................ 118 Power Supply Descriptions ......................... 118 Recommended Power Supply Connections.......................................... 118 Recommended Power Supply Filtering Scheme................................................. 118 Package Information ................................................ 120 Package Pinouts ......................................... 120 Package Thermal Characteristics Summary............ 148 ΘJA .............................................................. 148 ψJC .............................................................. 148 ΘJC .............................................................. 148 ΘJB .............................................................. 148 FPSC Maximum Junction Temperature ...... 149 Package Thermal Characteristics ............... 149 Heat Sink Vendors for BGA Packages........ 149 Package Parasitics...................................... 149 Package Outline Drawings .......................... 150 Part Number Description.......................................... 151 Device Type Options ................................... 151 Ordering Information ................................................ 151 Conventional Packaging ............................. 151 Lead-Free Packaging .................................. 152 |
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