V62C3801024L(L)

Parameter

Symbol

Test Condition

Min

Max

Unit

1.0

-

V

Data Retention Current

-

5

µA

Chip Deselect to Data Retention Time

0

-

ns

-

ns

Data Retention Mode

2.7V

2.7V

V

CC

CE

t

R

t

CDR

8

Notes

1. L-version includes this feature.

2. This Parameter is sampled and not 100% tested.

3. For test conditions, see AC Test Condition, Figure A.

4. This parameter is tested with CL = 5

pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is HIGH for read cycle.

7. CE1 and OE are LOW and CE2 is HIGH for read cycle.

8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.

9. All read cycle timings are referenced from the last valid address to the first transtion address.

10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

REV. 1.1 April 2001 V62C3801024L(L)