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LC4128ZE7MN144CES Datasheet(PDF) 24 Page - Lattice Semiconductor |
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LC4128ZE7MN144CES Datasheet(HTML) 24 Page - Lattice Semiconductor |
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24 / 54 page  Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 24 ispMACH 4000ZE Internal Timing Parameters Over Recommended Operating Conditions Parameter Description LC4032ZE LC4064ZE Units -4 -4 Min. Max. Min. Max. In/Out Delays tIN Input Buffer Delay — 0.85 — 0.90 ns tGCLK_IN Global Clock Input Buffer Delay — 1.60 — 1.60 ns tGOE Global OE Pin Delay — 2.25 — 2.25 ns tBUF Delay through Output Buffer — 0.75 — 0.90 ns tEN Output Enable Time — 2.25 — 2.25 ns tDIS Output Disable Time — 1.35 — 1.35 ns tPGSU Input Power Guard Setup Time — 3.30 — 3.55 ns tPGH Input Power Guard Hold Time — 0.00 — 0.00 ns tPGPW Input Power Guard BIE Minimum Pulse Width — 5.00 — 5.00 ns tPGRT Input Power Guard Recovery Time Following BIE Dissertation — 5.00 — 5.00 ns Routing Delays tROUTE Delay through GRP — 1.60 — 1.70 ns tPDi Macrocell Propagation Delay — 0.25 — 0.25 ns tMCELL Macrocell Delay — 0.65 — 0.65 ns tINREG Input Buffer to Macrocell Register Delay — 0.90 — 1.00 ns tFBK Internal Feedback Delay — 0.55 — 0.55 ns tORP Output Routing Pool Delay — 0.30 — 0.30 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 0.70 — 0.85 — ns tS_PT D-Register Setup Time (Product Term Clock) 1.25 — 1.85 — ns tH D-Register Hold Time 1.50 — 1.65 — ns tST T-Register Setup Time (Global Clock) 0.90 — 1.05 — ns tST_PT T-register Setup Time (Product Term Clock) 1.45 — 1.65 — ns tHT T-Resister Hold Time 1.50 — 1.65 — ns tSIR D-Input Register Setup Time (Global Clock) 0.85 — 0.80 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 1.15 — 1.30 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 0.90 — 1.10 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.35 — 0.40 ns tCES Clock Enable Setup Time 1.00 — 2.00 — ns tCEH Clock Enable Hold Time 0.00 — 0.00 — ns tSL Latch Setup Time (Global Clock) 0.70 — 0.95 — ns tSL_PT Latch Setup Time (Product Term Clock) 1.45 — 1.85 — ns tHL Latch Hold Time 1.40 — 1.80 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.40 — 0.35 ns tPDLi Propagation Delay through Transparent Latch to Output/ Feedback MUX — 0.30 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay — 0.30 — 0.30 ns |
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