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LC4256ZE7MN144CES Datasheet(PDF) 25 Page - Lattice Semiconductor |
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LC4256ZE7MN144CES Datasheet(HTML) 25 Page - Lattice Semiconductor |
25 / 54 page Lattice Semiconductor ispMACH 4000ZE Family Data Sheet 25 tSRR Asynchronous Reset or Set Recovery Delay — 2.00 — 1.70 ns Control Delays tBCLK GLB PT Clock Delay — 1.20 — 1.30 ns tPTCLK Macrocell PT Clock Delay — 1.40 — 1.50 ns tBSR Block PT Set/Reset Delay — 1.10 — 1.85 ns tPTSR Macrocell PT Set/Reset Delay — 1.20 — 1.90 ns tBIE Power Guard Block Input Enable Delay — 1.60 — 1.70 ns tPTOE Macrocell PT OE Delay — 2.30 — 3.15 ns tGPTOE Global PT OE Delay — 1.80 — 2.15 ns Internal Oscillator tOSCSU Oscillator DYNOSCDIS Setup Time 5.00 — 5.00 — ns tOSCH Oscillator DYNOSCDIS Hold Time 5.00 — 5.00 — ns tOSCEN Oscillator OSCOUT Enable Time (To Stable) — 5.00 — 5.00 ns tOSCOD Oscillator Output Delay — 4.00 — 4.00 ns tOSCNOM Oscillator OSCOUT Nominal Frequency 5.00 5.00 MHz tOSCvar Oscillator Variation of Nominal Frequency — 30 — 30 % tTMRCO20 Oscillator TIMEROUT Clock (Negative Edge) to Out (20-Bit Divider) — 12.50 — 12.50 ns tTMRCO10 Oscillator TIMEROUT Clock (Negative Edge) to Out (10-Bit Divider) — 7.50 — 7.50 ns tTMRCO7 Oscillator TIMEROUT Clock (Negative Edge) to Out (7-Bit Divider) — 6.00 — 6.00 ns tTMRRSTO Oscillator TIMEROUT Reset to Out (Going Low) — 5.00 — 5.00 ns tTMRRR Oscillator TIMEROUT Asynchronous Reset Recovery Delay — 4.00 — 4.00 ns tTMRRSTPW Oscillator TIMEROUT Reset Minimum Pulse Width 3.00 — 3.00 — ns Optional Delay Adjusters Base Parameter tINDIO Input Register Delay tINREG — 1.00 — 1.00 ns tEXP Product Term Expander Delay tMCELL — 0.40 — 0.40 ns tBLA Additional Block Loading Adders tROUTE — 0.04 — 0.05 ns tIOI Input Buffer Delays LVTTL_in Using LVTTL standard tIN, tGCLK_IN, tGOE — 0.60 — 0.60 ns LVCMOS15_in Using LVCMOS 1.5 Standard tIN, tGCLK_IN, tGOE — 0.20 — 0.20 ns LVCMOS18_in Using LVCMOS 1.8 Standard tIN, tGCLK_IN, tGOE — 0.00 — 0.00 ns LVCMOS25_in Using LVCMOS 2.5 Standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns LVCMOS33_in Using LVCMOS 3.3 Standard with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns PCI_in Using PCI Compatible Input with Hysteresis tIN, tGCLK_IN, tGOE — 0.80 — 0.80 ns tIOO Output Buffer Delays LVTTL_out Output Configured as TTL Buffer tEN, tDIS, tBUF — 0.20 — 0.20 ns LVCMOS15_out Output Configured as 1.5V Buffer tEN, tDIS, tBUF — 0.20 — 0.20 ns ispMACH 4000ZE Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description LC4032ZE LC4064ZE Units -4 -4 Min. Max. Min. Max. |
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