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LC4256ZE7MN48I Datasheet(PDF) 11 Page - Lattice Semiconductor

Part No. LC4256ZE7MN48I
Description  1.8V In-System Programmable Ultra Low Power PLDs
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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 11 page
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
11
Figure 9. Power Guard
All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a
Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external
sources using one of the user I/O or input pins.
Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled
on a pin-by-pin basis.
Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os.
Figure 10. Power Guard and BIE in a Block with 8 I/Os
0
1
E
Q
D
Power Guard
Power Guard
To Macrocell
I/O 0
I/O 1
I/O 7
To GRP
0
1
To Macrocell
To GRP
To Macrocell
To GRP
Block Input Enable (BIE)
From Block PT. The Block PT
is part of the block AND Array,
and can be driven by signals
from the GRP.
Power Guard
Power Guard
0
1
0
1




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