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LC4256ZE5TN100I Datasheet(PDF) 10 Page - Lattice Semiconductor

Part No. LC4256ZE5TN100I
Description  1.8V In-System Programmable Ultra Low Power PLDs
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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 10 page
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:
• LVTTL
• LVCMOS 1.8
• LVCMOS 3.3
• LVCMOS 1.5
• LVCMOS 2.5
• 3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down
resistor selectable on a “per-pin” basis. A fourth option is to provide none of these. The default in both hardware
and software is such that when the device is erased or if the user does not specify, the input structure is configured
to be a Pull-down Resistor.
Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can
be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew
setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer
reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated
lines, the fast slew rate can be used to achieve the highest speed.
The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and
2.5V. This provides improved noise immunity for slow transitioning signals.
Power Guard
Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature con-
sists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device.
If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were
toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal
dynamic power consumption.
To Macrocell
To GRP
VCCO
GOE 0
GOE 1
GOE 2
GOE 3
VCC
From ORP
From ORP
0
1
Block Input Enable (BIE)
(From Block PT)
Power Guard Disable Fuse (PGDF)
0
1
Power Guard
I/O Bus Maintenance
VCCO




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