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LC4128ZE7TN48C Datasheet(PDF) 23 Page - Lattice Semiconductor

Part # LC4128ZE7TN48C
Description  1.8V In-System Programmable Ultra Low Power PLDs
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC4128ZE7TN48C Datasheet(HTML) 23 Page - Lattice Semiconductor

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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
23
Timing Model
The task of determining the timing through the ispMACH 4000ZE family, like any CPLD, is relatively simple. The
timing model provided in Figure 16 shows the specific delay paths. Once the implementation of a given function is
determined either conceptually or from the software report file, the delay path of the function can easily be deter-
mined from the timing model. The Lattice design tools report the timing delays based on the same timing model for
a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The
external timing parameters are tested and guaranteed for every device. For more information on the timing model
and usage, please refer to technical note TN1168, ispMACH 4000ZE Timing Model Design and Usage Guidelines.
Figure 16. ispMACH 4000ZE Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
Oscillator/ Timer
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
tFBK
Feedback
Feedback
From
Feedback
tBUF
tMCELL
tPTCLK
tBCLK
tPTSR
tBIE
tBSR
tGPTOE
tPTOE
tEXP
tROUTE
tOSCDIS
tOSCEN
tOSCOD
tBLA
tINREG
tINDIO
tIN
tPGRT
tIOI
tGCLK_IN
tIOI
tPGRT
tPGRT
tGOE
tIOI
tPDi
tIOO
tORP
tEN
tDIS


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