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LC4512B-5F256C1 Datasheet(PDF) 33 Page - Lattice Semiconductor |
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LC4512B-5F256C1 Datasheet(HTML) 33 Page - Lattice Semiconductor |
33 / 99 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 33 ispMACH 4000Z Internal Timing Parameters (Cont.) Over Recommended Operating Conditions Parameter Description -45 -5 -75 Units Min. Max. Min. Max. Min. Max. In/Out Delays tIN Input Buffer Delay — 0.95 — 1.25 — 1.80 ns tGOE Global OE Pin Delay — 3.00 — 3.50 — 4.30 ns tGCLK_IN Global Clock Input Buffer Delay — 1.95 — 2.05 — 2.15 ns tBUF Delay through Output Buffer — 1.10 — 1.00 — 1.30 ns tEN Output Enable Time — 2.50 — 2.50 — 2.70 ns tDIS Output Disable Time — 2.50 — 2.50 — 2.70 ns Routing/GLB Delays tROUTE Delay through GRP — 2.25 — 2.05 — 2.50 ns tMCELL Macrocell Delay — 0.65 — 0.65 — 1.00 ns tINREG Input Buffer to Macrocell Register Delay — 1.00 — 1.00 — 1.00 ns tFBK Internal Feedback Delay — 0.35 — 0.05 — 0.05 ns tPDb 5-PT Bypass Propagation Delay — 0.20 — 0.70 — 1.90 ns tPDi Macrocell Propagation Delay — 0.45 — 0.65 — 1.00 ns Register/Latch Delays tS D-Register Setup Time (Global Clock) 1.00 — 1.10 — 1.35 — ns tS_PT D-Register Setup Time (Product Term Clock) 2.10 — 1.90 — 2.45 — ns tST T-Register Setup Time (Global Clock) 1.20 — 1.30 — 1.55 — ns tST_PT T-register Setup Time (Product Term Clock) 2.30 — 2.10 — 2.75 — ns tH D-Register Hold Time 1.90 — 1.90 — 3.15 — ns tHT T-Resister Hold Time 1.90 — 1.90 — 3.15 — ns tSIR D-Input Register Setup Time (Global Clock) 1.30 — 1.10 — 0.75 — ns tSIR_PT D-Input Register Setup Time (Product Term Clock) 1.45 — 1.45 — 1.45 — ns tHIR D-Input Register Hold Time (Global Clock) 1.30 — 1.50 — 1.95 — ns tHIR_PT D-Input Register Hold Time (Product Term Clock) 1.00 — 1.00 — 1.18 — ns tCOi Register Clock to Output/Feedback MUX Time — 0.75 — 1.15 — 1.05 ns tCES Clock Enable Setup Time 2.00 — 2.00 — 2.00 — ns tCEH Clock Enable Hold Time 0.00 — 0.00 — 0.00 — ns tSL Latch Setup Time (Global Clock) 1.00 — 1.00 — 1.65 — ns tSL_PT Latch Setup Time (Product Term Clock) 2.10 — 1.90 — 2.15 — ns tHL Latch Hold Time 2.00 — 2.00 — 1.17 — ns tGOi Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 — 0.33 ns tPDLi Propagation Delay through Transparent Latch to Output/ Feedback MUX — 0.25 — 0.25 — 0.25 ns tSRi Asynchronous Reset or Set to Output/Feedback MUX Delay — 0.97 — 0.97 — 0.28 ns tSRR Asynchronous Reset or Set Recovery Delay — 1.80 — 1.80 — 1.67 ns Control Delays tBCLK GLB PT Clock Delay — 1.55 — 1.55 — 1.25 ns tPTCLK Macrocell PT Clock Delay — 1.55 — 1.55 — 1.25 ns tBSR GLB PT Set/Reset Delay — 1.83 — 1.83 — 1.83 ns tPTSR Macrocell PT Set/Reset Delay — 1.83 — 1.83 — 2.72 ns tGPTOE Global PT OE Delay — 4.30 — 4.20 — 3.50 ns |
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Similar Description - LC4512B-5F256C1 |
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