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LC5512MC-75F256I Datasheet(PDF) 23 Page - Lattice Semiconductor |
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LC5512MC-75F256I Datasheet(HTML) 23 Page - Lattice Semiconductor |
23 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 23 DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units IIL, IIH 1 Input or I/O Leakage 0 ≤ VIN ≤ (VCCO - 0.2V) — — 10 µA (VCCO - 0.2V) < VIN ≤ 3.6V — — 40 µA IIH 4 Input High Leakage Current 3.6V < VIN ≤ 5.5V and 3.0V ≤ VCCO ≤ 3.6V —— 3 mA IPU 3 I/O Active Pullup Current 0 ≤ VIN ≤ 0.7 VCCO -30 — -150 µA IPD I/O Active Pulldown Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 150 µA IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCO 30 — — µA IBHLO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VIH (MAX) — — 150 µA IBHHO Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX) — — 150 µA VBHT Bus Hold Trip Points 0 ≤ VIN ≤ VIH (MAX) VCCO * 0.35 — VCCO * 0.65 µA C1 I/O Capacitance 2 VCCO = 3.3V, 2.5V, 1.8V — 8 — pf VCC = 1.8V, VIO = 0 to VIH (MAX) — 8 — pf C2 Clock Capacitance 2 VCCO = 3.3V, 2.5V, 1.8V — 8 — pf VCC = 1.8V, VIO = 0 to VIH (MAX) — 8 — pf C3 Global Input Capacitance 2 VCCO = 3.3V, 2.5V, 1.8V — 8 — pf VCC = 1.8V, VIO = 0 to VIH (MAX) — 8 — pf 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25°C, f=1.0MHz 3. IPU on JTAG pins has a maximum of -175µA for 5512MX devices. 4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. The JTAG and sysCONFIG ports are not included for the 5V tolerant interface. |
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