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LC5512MC-5Q256I Datasheet(PDF) 32 Page - Lattice Semiconductor

Part # LC5512MC-5Q256I
Description  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC5512MC-5Q256I Datasheet(HTML) 32 Page - Lattice Semiconductor

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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
32
ispXPLD 5000MX Family Internal Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
In/Out Delays
tIN
Input Buffer Delay
0.70
0.91
0.96
1.11
1.30
ns
tGCLK_IN
Global Clock Input
Buffer Delay
0.40
0.35
0.35
0.35
0.55
ns
tRST
Global RESET Pin
Delay
3.77
4.24
4.71
4.71
7.07
ns
tGOE
Global OE Pin
Delay
1.98
2.66
2.34
2.87
3.27
ns
tBUF
Delay through
Output Buffer
1.16
1.30
1.45
1.60
2.17
ns
tEN
Output Enable Time
2.52
2.84
3.16
3.63
4.23
ns
tDIS
Output Disable
Time
1.92
2.40
2.40
2.40
3.60
ns
Routing Delays
tROUTE
Delay through SRP
1.95
2.06
2.34
2.24
3.66
ns
tINREG
Input Buffer to
Macrocell Register
Delay
0.60
0.60
0.60
0.47
1.63
ns
tPTSA
Product Term
Sharing Array Delay
0.50
0.50
0.53
0.83
1.34
ns
tFBK
Internal Feedback
Delay
0.19
0.02
0.39
0.03
0.60
ns
tGCLK
Global Clock Tree
Delay
0.52
0.32
0.72
0.82
0.78
ns
tBCLK
Block PT Clock
Delay
0.12
0.14
0.15
0.15
0.23
ns
tPTCLK
Macrocell PT Clock
Delay
0.12
0.14
0.15
0.15
0.23
ns
tPLL_DELAY
Programmable PLL
Delay Increment
0.30
0.30
0.30
0.30
0.30
ns
tBSR
Block PT Reset
Delay
0.72
0.81
0.90
0.94
1.35
ns
tPTSR
Macrocell PT Set/
Reset Delay
0.60
0.75
0.75
0.75
1.13
ns
tLPTOE
Macrocell PT OE
Delay
0.83
1.19
1.04
1.52
1.31
ns
tSPTOE
Segment PT OE
Delay
0.83
1.19
1.04
1.52
1.31
ns
tOSA
Output Sharing
Array Delay
0.80
0.90
1.00
1.00
1.50
ns
tPTOE
Global PT OE Delay
0.83
1.04
1.04
1.04
1.56
ns
tPDB
5-PT Bypass
Propagation Delay
0.20
0.23
0.25
0.25
0.38
ns
tPDI
Macrocell
Propagation Delay
0.50
0.93
0.72
0.72
1.04
ns


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