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LC5512MC-75Q256I Datasheet(PDF) 63 Page - Lattice Semiconductor |
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LC5512MC-75Q256I Datasheet(HTML) 63 Page - Lattice Semiconductor |
63 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 63 0 96N M12 M23 O23 M13 196 B5 A10 0 96P M10 M22 O22 M11 197 A3 A9 0 97N M8 M21 O21 M9 198 B4 C9 0 97P M6 M20 O20 M7 199 B3 D9 0 98N M5 M19 O19 — 200 C5 F9 0 98P M4 M18 O18 — 201 C6 E9 0 99N M2 M1 O1 M3 202 D5 A8 —— VCCO0 —— — — VCCO0 VCCO0 0 99P M0 M0 O0 M1 203 D6 B8 — — GND (Bank 0) — — — — GND (Bank 0) GND (Bank 0) 0 100N N30 O29 — N31 — — A7 0 100P N28 O28 — N29 — — B7 0 101N N26 O27 — N27 — — A5 0 101P N24 O26 — N25 — — B5 0 102N N22 O25 — N23 — — B6 0 102P N21 O24 — — — — C7 0 103N N20 O23 — — — — E8 0 103P N18 O22 — N19 — — E7 0 104N N16 O21 — N17 — — E6 0 104P N14 O20 — N15 — — D6 0 105N N12 O19 — N13 — — D8 —— VCCO0 — — — 204 VCCO0 VCCO0 0 105P N10 O18 — N11 — — F8 — — GND (Bank 0) — — — 205 GND (Bank 0) GND (Bank 0) 0 106N N8 O17 — N9 — — F7 0 106P N6 O16 — N7 — — D7 0 107N N5 O15 — — 206 A2 C6 0 107P N4 O14 — — 207 B2 C5 0 108N N2 O13 — N3 — — C4 0 108P N0 O12 — N1 — — D5 1. Not available for differential pair. Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs. ispXPLD 5512MX Logic Signal Connections (Continued) sysIO Bank LVDS Pair Primary Macrocell/ Function Alternate Outputs Alternate Input 208 PQFP Pin Number 256 fpBGA Ball Number 484 fpBGA Ball Number Macrocell 1 Macrocell 2 |
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