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LC4384V-5F256I1 Datasheet(PDF) 24 Page - Lattice Semiconductor |
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LC4384V-5F256I1 Datasheet(HTML) 24 Page - Lattice Semiconductor |
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24 / 99 page  Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 24 ispMACH 4000Z External Switching Characteristics Over Recommended Operating Conditions Parameter Description 1, 2, 3 -35 -37 -42 Units Min. Max. Min. Max. Min. Max. tPD 5-PT bypass combinatorial propagation delay — 3.5 — 3.7 — 4.2 ns tPD_MC 20-PT combinatorial propagation delay through macrocell — 4.4 — 4.7 — 5.7 ns tS GLB register setup time before clock 2.2 — 2.5 — 2.7 — ns tST GLB register setup time before clock with T-type register 2.4 — 2.7 — 2.9 — ns tSIR GLB register setup time before clock, input register path 1.0 — 1.1 — 1.3 — ns tSIRZ GLB register setup time before clock with zero hold 2.0 — 2.1 — 2.6 — ns tH GLB register hold time after clock 0.0 — 0.0 — 0.0 — ns tHT GLB register hold time after clock with T-type register 0.0 — 0.0 — 0.0 — ns tHIR GLB register hold time after clock, input register path 1.0 — 1.0 — 1.3 — ns tHIRZ GLB register hold time after clock, input register path with zero hold 0.0 — 0.0 — 0.0 — ns tCO GLB register clock-to-output delay — 3.0 — 3.2 — 3.5 ns tR External reset pin to output delay — 5.0 — 6.0 — 7.3 ns tRW External reset pulse duration 1.5 — 1.7 — 2.0 — ns tPTOE/DIS Input to output local product term output enable/disable — 7.0 — 8.0 — 8.0 ns tGPTOE/DIS Input to output global product term output enable/disable — 6.5 — 7.0 — 8.0 ns tGOE/DIS Global OE input to output enable/disable — 4.5 — 4.5 — 4.8 ns tCW Global clock width, high or low 1.0 — 1.5 — 1.8 — ns tGW Global gate width low (for low transparent) or high (for high transparent) 1.0 — 1.5 — 1.8 — ns tWIR Input register clock width, high or low 1.0 — 1.5 — 1.8 — ns fMAX 4 Clock frequency with internal feedback 267 — 250 — 220 — MHz tMAX (Ext.) clock frequency with external feedback, [1 / (tS + tCO)] 192 — 175 — 161 — MHz 1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.2.2 2. Measured using standard switching GRP loading of 1 and 1 output switching. 3. Pulse widths and clock widths less than minimum will cause unknown behavior. 4. Standard 16-bit counter using GRP feedback. |
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