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AD7625 Datasheet(PDF) 1 Page - Analog Devices |
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AD7625 Datasheet(HTML) 1 Page - Analog Devices |
1 / 11 page 16-Bit, 6MSPS PulSAR Differential ADC Preliminary Technical Data AD7625 Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. FEATURES Throughput: 6 MSPS SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB Min @ 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay (SAR architecture) Serial LVDS interface: Self-clocked mode Echoed-clock mode Reference: Internal 4.096 V External (1.2V) buffered to 4.096 V External 4.096 V Power dissipation 150 mW 32-Lead LFCSP package (5 mm x 5 mm) APPLICATIONS High dynamic range telecommunications Receivers Digital imaging systems High-speed data acquisition Spectrum analysis Test equipment Table 1. Fast PulSAR ADC Selection Input Type Res (Bit s) ≥1 MSPS to < 2MSPS ≥ 2 MSPS to ≤ 3 MSPS 6 MSPS 10 MSPS Differential (ground sense) 16 AD7653 AD7667 AD7980 AD7983 AD7985 True Bipolar 16 AD7671 Differential (anti-phase) 16 AD7677 AD7623 AD7621 AD7622 AD7625 AD7626 Differential (anti-phase) 18 AD7643 AD7982 AD7984 AD7641 AD7986 FUNCTIONAL BLOCK DIAGRAM AD7626 CLOCK LOGIC SERIAL LVDS IN- IN+ REFIN REF VCM SAR 2 CNV VIO D DCO CLK 1.2V BANDGAP CAP DAC Figure 1. GENERAL DESCRIPTION The AD7625 is a 16-bit, 6MSPS, charge redistribution successive approximation register (SAR) architecture, analog-to-digital converter (ADC). SAR architecture allows unmatched performance both in noise – 92dB SNR - and in linearity – 1LSB. The AD7625 contains a high speed 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV edge, it samples the voltage difference between IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or echoed-clock serial interface reducing external hardware connections. The AD7625 is housed in a 32-lead LFCSP (5mm by 5mm) with operation specified from −40°C to +85°C. |
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