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LC4256ZC-75TN176C Datasheet(PDF) 12 Page - Lattice Semiconductor |
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LC4256ZC-75TN176C Datasheet(HTML) 12 Page - Lattice Semiconductor |
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12 / 99 page  Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 12 • LVTTL • LVCMOS 1.8 • LVCMOS 3.3 • 3.3V PCI Compatible • LVCMOS 2.5 All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both hardware and software is such that when the device is erased or if the user does not specify, the input structure is configured to be a Pull-up Resistor. Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set- ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflec- tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. Global OE Generation Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a 2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted. Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a 256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10 show a graphical representation of the global OE generation. Figure 9. Global OE Generation for All Devices Except ispMACH 4032 Shared PTOE (Block 0) Shared PTOE (Block n) Global Fuses GOE (0:3) to I/O cells Internal Global OE PT Bus (4 lines) 4-Bit Global OE Bus Global OE Fuse connection Hard wired |
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