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LC4256ZC-75MN132I Datasheet(PDF) 27 Page - Lattice Semiconductor

Part # LC4256ZC-75MN132I
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC4256ZC-75MN132I Datasheet(HTML) 27 Page - Lattice Semiconductor

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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
27
ispMACH 4000V/B/C Internal Timing Parameters
Over Recommended Operating Conditions
Parameter
Description
-2.5
-2.7
-3
-3.5
Units
In/Out Delays
tIN
Input Buffer Delay
0.60
0.60
0.70
0.70
ns
tGOE
Global OE Pin Delay
2.04
2.54
3.04
3.54
ns
tGCLK_IN
Global Clock Input Buffer Delay
0.78
1.28
1.28
1.28
ns
tBUF
Delay through Output Buffer
0.85
0.85
0.85
0.85
ns
tEN
Output Enable Time
0.96
0.96
0.96
0.96
ns
tDIS
Output Disable Time
0.96
0.96
0.96
0.96
ns
Routing/GLB Delays
tROUTE
Delay through GRP
0.61
0.81
1.01
1.01
ns
tMCELL
Macrocell Delay
0.45
0.55
0.55
0.65
ns
tINREG
Input Buffer to Macrocell Register
Delay
0.11
0.31
0.31
0.31
ns
tFBK
Internal Feedback Delay
0.00
0.00
0.00
0.00
ns
tPDb
5-PT Bypass Propagation Delay
0.44
0.44
0.44
0.94
ns
tPDi
Macrocell Propagation Delay
0.64
0.64
0.64
0.94
ns
Register/Latch Delays
tS
D-Register Setup Time
(Global Clock)
0.92
1.12
1.02
0.92
ns
tS_PT
D-Register Setup Time
(Product Term Clock)
1.42
1.32
1.32
1.32
ns
tST
T-Register Setup Time
(Global Clock)
1.12
1.32
1.22
1.12
ns
tST_PT
T-Register Setup Time
(Product Term Clock)
1.42
1.32
1.32
1.32
ns
tH
D-Register Hold Time
0.88
0.68
0.98
1.08
ns
tHT
T-Register Hold Time
0.88
0.68
0.98
1.08
ns
tSIR
D-Input Register Setup Time
(Global Clock)
0.82
1.37
1.27
1.27
ns
tSIR_PT
D-Input Register Setup Time
(Product Term Clock)
1.45
1.45
1.45
1.45
ns
tHIR
D-Input Register Hold Time
(Global Clock)
0.88
0.63
0.73
0.73
ns
tHIR_PT
D-Input Register Hold Time
(Product Term Clock)
0.88
0.63
0.73
0.73
ns
tCOi
Register Clock to Output/Feedback
MUX Time
0.52
0.52
0.52
0.52
ns
tCES
Clock Enable Setup Time
2.25
2.25
2.25
2.25
ns
tCEH
Clock Enable Hold Time
1.88
1.88
1.88
1.88
ns
tSL
Latch Setup Time
(Global Clock)
0.92
1.12
1.02
0.92
ns
tSL_PT
Latch Setup Time (Product Term
Clock)
1.42
1.32
1.32
1.32
ns
tHL
Latch Hold Time
1.17
1.17
1.17
1.17
ns
tGOi
Latch Gate to Output/Feedback
MUX Time
0.33
0.33
0.33
0.33
ns


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