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LC4256C-75FTN256AI Datasheet(PDF) 6 Page - Lattice Semiconductor

Part No. LC4256C-75FTN256AI
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
6
Product Term Allocator
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 3. Individual PT Steering
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 4. Available Clusters for Each Macrocell
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.
Product Term
Logic
Control
PT
n
Logic PT
Single PT for XOR/OR
PT
n+1
Logic PT
Individual Clock (PT Clock)
PT
n+2
Logic PT
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
PT
n+3
Logic PT
Individual Initialization (PT Initialization)
PT
n+4
Logic PT
Individual OE (PTOE)
Macrocell
Available Clusters
M0
—
C0C1C2
M1
C0
C1
C2
C3
M2
C1
C2
C3
C4
M3
C2
C3
C4
C5
M4
C3
C4
C5
C6
M5
C4
C5
C6
C7
M6
C5
C6
C7
C8
M7
C6
C7
C8
C9
M8
C7
C8
C9
C10
M9
C8
C9
C10
C11
M10
C9
C10
C11
C12
M11
C10
C11
C12
C13
M12
C11
C12
C13
C14
M13
C12
C13
C14
C15
M14
C13
C14
C15
—
M15
C14
C15
—
—




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