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LC4384B-75TN176C Datasheet(PDF) 23 Page - Lattice Semiconductor |
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LC4384B-75TN176C Datasheet(HTML) 23 Page - Lattice Semiconductor |
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23 / 99 page  Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 23 ispMACH 4000V/B/C External Switching Characteristics (Cont.) Over Recommended Operating Conditions Parameter Description 1, 2, 3 -5 -75 -10 Units Min. Max. Min. Max. Min. Max. tPD 5-PT bypass combinatorial propagation delay — 5.0 — 7.5 — 10.0 ns tPD_MC 20-PT combinatorial propagation delay through macrocell — 5.5 — 8.0 — 10.5 ns tS GLB register setup time before clock 3.0 — 4.5 — 5.5 — ns tST GLB register setup time before clock with T-type register 3.2 — 4.7 — 5.5 — ns tSIR GLB register setup time before clock, input register path 1.2 — 1.7 — 1.7 — ns tSIRZ GLB register setup time before clock with zero hold 2.2 — 2.7 — 2.7 — ns tH GLB register hold time after clock 0.0 — 0.0 — 0.0 — ns tHT GLB register hold time after clock with T-type register 0.0 — 0.0 — 0.0 — ns tHIR GLB register hold time after clock, input register path 1.0 — 1.0 — 1.0 — ns tHIRZ GLB register hold time after clock, input register path with zero hold 0.0 — 0.0 — 0.0 — ns tCO GLB register clock-to-output delay — 3.4 — 4.5 — 6.0 ns tR External reset pin to output delay — 6.3 — 9.0 — 10.5 ns tRW External reset pulse duration 2.0 — 4.0 — 4.0 — ns tPTOE/DIS Input to output local product term output enable/disable — 7.0 — 9.0 — 10.5 ns tGPTOE/DIS Input to output global product term output enable/disable — 9.0 — 10.3 — 12.0 ns tGOE/DIS Global OE input to output enable/disable — 5.0 — 7.0 — 8.0 ns tCW Global clock width, high or low 2.2 — 3.3 — 4.0 — ns tGW Global gate width low (for low transparent) or high (for high transparent) 2.2 — 3.3 — 4.0 — ns tWIR Input register clock width, high or low 2.2 — 3.3 — 4.0 — ns fMAX 4 Clock frequency with internal feedback 227 — 168 — 125 — MHz fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)] 156 — 111 — 86 — MHz 1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.3.2 2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching. 3. Pulse widths and clock widths less than minimum will cause unknown behavior. 4. Standard 16-bit counter using GRP feedback. |
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