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LC4256B-10FTN256AI Datasheet(PDF) 39 Page - Lattice Semiconductor

Part # LC4256B-10FTN256AI
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC4256B-10FTN256AI Datasheet(HTML) 39 Page - Lattice Semiconductor

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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
39
Boundary Scan Waveforms and Timing Specifications
Symbol
Parameter
Min.
Max.
Units
tBTCP
TCK [BSCAN test] clock cycle
40
ns
tBTCH
TCK [BSCAN test] pulse width high
20
ns
tBTCL
TCK [BSCAN test] pulse width low
20
ns
tBTSU
TCK [BSCAN test] setup time
8
ns
tBTH
TCK [BSCAN test] hold time
10
ns
tBRF
TCK [BSCAN test] rise and fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
10
ns
tBTOZ
TAP controller falling edge of clock to data output disable
10
ns
tBTVO
TAP controller falling edge of clock to data output enable
10
ns
tBTCPSU
BSCAN test Capture register setup time
8
ns
tBTCPH
BSCAN test Capture register hold time
10
ns
tBTUCO
BSCAN test Update reg, falling edge of clock to valid output
25
ns
tBTUOZ
BSCAN test Update reg, falling edge of clock to output disable
25
ns
tBTUOV
BSCAN test Update reg, falling edge of clock to output enable
25
ns


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