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LC5512MC-75FN672I Datasheet(PDF) 45 Page - Lattice Semiconductor

Part # LC5512MC-75FN672I
Description  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC5512MC-75FN672I Datasheet(HTML) 45 Page - Lattice Semiconductor

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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
45
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
Max
Units
tBTCP
TCK [BSCAN] clock pulse width
40
ns
tBTCPH
TCK [BSCAN] clock pulse width high
20
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
ns
tBTS
TCK [BSCAN] setup time
8
ns
tBTH
TCK [BSCAN] hold time
10
ns
tBTRF
TCK [BSCAN] rise/fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
10
ns
tBTCODIS
TAP controller falling edge of clock to valid disable
10
ns
tBTCOEN
TAP controller falling edge of clock to valid enable
10
ns
tBTCRS
BSCAN test capture register setup time
8
ns
tBTCRH
BSCAN test capture register hold time
10
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
25
ns


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