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LC4512B-5FN256I1 Datasheet(PDF) 38 Page - Lattice Semiconductor |
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LC4512B-5FN256I1 Datasheet(HTML) 38 Page - Lattice Semiconductor |
38 / 99 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 38 ispMACH 4000Z Timing Adders (Cont.) 1 Adder Type Base Parameter Description -45 -5 -75 Units Min. Max. Min. Max. Min. Max. Optional Delay Adders tINDIO tINREG Input register delay — 1.30 — 1.30 — 1.30 ns tEXP tMCELL Product term expander delay — 0.45 — 0.45 — 0.50 ns tORP — Output routing pool delay — 0.40 — 0.40 — 0.40 ns tBLA tROUTE Additional block load- ing adder — 0.05 — 0.05 — 0.05 ns tIOI Input Adjusters LVTTL_in tIN, tGCLK_IN, tGOE Using LVTTL standard — 0.60 — 0.60 — 0.60 ns LVCMOS33_in tIN, tGCLK_IN, tGOE Using LVCMOS 3.3 standard — 0.60 — 0.60 — 0.60 ns LVCMOS25_in tIN, tGCLK_IN, tGOE Using LVCMOS 2.5 standard — 0.60 — 0.60 — 0.60 ns LVCMOS18_in tIN, tGCLK_IN, tGOE Using LVCMOS 1.8 standard — 0.00 — 0.00 — 0.00 ns PCI_in tIN, tGCLK_IN, tGOE Using PCI compatible input — 0.60 — 0.60 — 0.60 ns tIOO Output Adjusters LVTTL_out tBUF, tEN, tDIS Output configured as TTL buffer — 0.20 — 0.20 — 0.20 ns LVCMOS33_out tBUF, tEN, tDIS Output configured as 3.3V buffer — 0.20 — 0.20 — 0.20 ns LVCMOS25_out tBUF, tEN, tDIS Output configured as 2.5V buffer — 0.10 — 0.10 — 0.10 ns LVCMOS18_out tBUF, tEN, tDIS Output configured as 1.8V buffer — 0.00 — 0.00 — 0.00 ns PCI_out tBUF, tEN, tDIS Output configured as PCI compatible buffer — 0.20 — 0.20 — 0.20 ns Slow Slew tBUF, tEN Output configured for slow slew rate — 1.00 — 1.00 — 1.00 ns Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.2.2 1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders. |
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