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LC5512MC-75Q672I Datasheet(PDF) 13 Page - Lattice Semiconductor |
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LC5512MC-75Q672I Datasheet(HTML) 13 Page - Lattice Semiconductor |
13 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 13 FIFO Mode In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The read and write clocks can be different or the same dependent on the application. Four flags show the status of the FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro- grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica- tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read address. In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 12 shows the block diagram of the FIFO. Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg- isters. Figure 12. FIFO Block Diagram Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode Register Input Source Write Data, Write Enable Clock WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. Clock Enable WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Reset N/A Full and Almost Full Flags Clock WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. Clock Enable WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Reset Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired. Read Data, Empty and Almost Empty Flags Clock RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required. Clock Enable RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required. Reset Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction array from GRP, with inversion if desired. ‘ ‘ 68 Inputs From Routing Write Clock (WCLK) Write Enable (WE) Reset (RST) Read Enable (RE) Read Clock (RCLK) Reset_RP (RSTRP) Write Data (DI[0:0-31]) 16,384-bit SRAM Array FIFO Control Logic *Control logic can be duplicated in adjacent MFB in 32-bit mode RESET CLK0 CLK3 CLK1 CLK2 Read Data (DO[0:0-31]) FIFO Flags* Full, Empty, Almost Full, Almost Empty |
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