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LC4256V-3TN144C Datasheet(HTML) 25 Page - Lattice Semiconductor

Part No. LC4256V-3TN144C
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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LC4256V-3TN144C Datasheet(HTML) 25 Page - Lattice Semiconductor

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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
25
ispMACH 4000Z External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
-45
-5
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
tPD
5-PT bypass combinatorial propagation delay
4.5
5.0
7.5
ns
tPD_MC
20-PT combinatorial propagation delay
through macrocell
5.8
6.0
8.0
ns
tS
GLB register setup time before clock
2.9
3.0
4.5
ns
tST
GLB register setup time before clock with T-
type register
3.1
3.2
4.7
ns
tSIR
GLB register setup time before clock, input
register path
1.3
1.3
1.4
ns
tSIRZ
GLB register setup time before clock with zero
hold
2.6
2.6
2.7
ns
tH
GLB register hold time after clock
0.0
0.0
0.0
ns
tHT
GLB register hold time after clock with T-type
register
0.0
0.0
0.0
ns
tHIR
GLB register hold time after clock, input regis-
ter path
1.3
1.3
1.3
ns
tHIRZ
GLB register hold time after clock, input regis-
ter path with zero hold
0.0
0.0
0.0
ns
tCO
GLB register clock-to-output delay
3.8
4.2
4.5
ns
tR
External reset pin to output delay
7.5
7.5
9.0
ns
tRW
External reset pulse duration
2.0
2.0
4.0
ns
tPTOE/DIS
Input to output local product term output
enable/disable
8.2
8.5
9.0
ns
tGPTOE/DIS
Input to output global product term output
enable/disable
10.0
10.0
10.5
ns
tGOE/DIS
Global OE input to output enable/disable
5.5
6.0
7.0
ns
tCW
Global clock width, high or low
1.8
2.0
3.3
ns
tGW
Global gate width low (for low transparent) or
high (for high transparent)
1.8
2.0
3.3
ns
tWIR
Input register clock width, high or low
1.8
2.0
3.3
ns
fMAX
4
Clock frequency with internal feedback
200
200
168
MHz
tMAX (Ext.)
clock frequency with external feedback, [1 /
(tS + tCO)]
150
139
111
MHz
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
Timing v.2.2
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.


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