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LC4256V-75FTN256BI Datasheet(PDF) 27 Page - Lattice Semiconductor

Part No. LC4256V-75FTN256BI
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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 27 page
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
27
ispMACH 4000V/B/C Internal Timing Parameters
Over Recommended Operating Conditions
Parameter
Description
-2.5
-2.7
-3
-3.5
Units
In/Out Delays
tIN
Input Buffer Delay
β€”
0.60
β€”
0.60
β€”
0.70
β€”
0.70
ns
tGOE
Global OE Pin Delay
β€”
2.04
β€”
2.54
β€”
3.04
β€”
3.54
ns
tGCLK_IN
Global Clock Input Buffer Delay
β€”
0.78
β€”
1.28
β€”
1.28
β€”
1.28
ns
tBUF
Delay through Output Buffer
β€”
0.85
β€”
0.85
β€”
0.85
β€”
0.85
ns
tEN
Output Enable Time
β€”
0.96
β€”
0.96
β€”
0.96
β€”
0.96
ns
tDIS
Output Disable Time
β€”
0.96
β€”
0.96
β€”
0.96
β€”
0.96
ns
Routing/GLB Delays
tROUTE
Delay through GRP
β€”
0.61
β€”
0.81
β€”
1.01
β€”
1.01
ns
tMCELL
Macrocell Delay
β€”
0.45
β€”
0.55
β€”
0.55
β€”
0.65
ns
tINREG
Input Buffer to Macrocell Register
Delay
β€”
0.11
β€”
0.31
β€”
0.31
β€”
0.31
ns
tFBK
Internal Feedback Delay
β€”
0.00
β€”
0.00
β€”
0.00
β€”
0.00
ns
tPDb
5-PT Bypass Propagation Delay
β€”
0.44
β€”
0.44
β€”
0.44
β€”
0.94
ns
tPDi
Macrocell Propagation Delay
β€”
0.64
β€”
0.64
β€”
0.64
β€”
0.94
ns
Register/Latch Delays
tS
D-Register Setup Time
(Global Clock)
0.92
β€”
1.12
β€”
1.02
β€”
0.92
β€”
ns
tS_PT
D-Register Setup Time
(Product Term Clock)
1.42
β€”
1.32
β€”
1.32
β€”
1.32
β€”
ns
tST
T-Register Setup Time
(Global Clock)
1.12
β€”
1.32
β€”
1.22
β€”
1.12
β€”
ns
tST_PT
T-Register Setup Time
(Product Term Clock)
1.42
β€”
1.32
β€”
1.32
β€”
1.32
β€”
ns
tH
D-Register Hold Time
0.88
β€”
0.68
β€”
0.98
β€”
1.08
β€”
ns
tHT
T-Register Hold Time
0.88
β€”
0.68
β€”
0.98
β€”
1.08
β€”
ns
tSIR
D-Input Register Setup Time
(Global Clock)
0.82
β€”
1.37
β€”
1.27
β€”
1.27
β€”
ns
tSIR_PT
D-Input Register Setup Time
(Product Term Clock)
1.45
β€”
1.45
β€”
1.45
β€”
1.45
β€”
ns
tHIR
D-Input Register Hold Time
(Global Clock)
0.88
β€”
0.63
β€”
0.73
β€”
0.73
β€”
ns
tHIR_PT
D-Input Register Hold Time
(Product Term Clock)
0.88
β€”
0.63
β€”
0.73
β€”
0.73
β€”
ns
tCOi
Register Clock to Output/Feedback
MUX Time
β€”
0.52
β€”
0.52
β€”
0.52
β€”
0.52
ns
tCES
Clock Enable Setup Time
2.25
β€”
2.25
β€”
2.25
β€”
2.25
β€”
ns
tCEH
Clock Enable Hold Time
1.88
β€”
1.88
β€”
1.88
β€”
1.88
β€”
ns
tSL
Latch Setup Time
(Global Clock)
0.92
β€”
1.12
β€”
1.02
β€”
0.92
β€”
ns
tSL_PT
Latch Setup Time (Product Term
Clock)
1.42
β€”
1.32
β€”
1.32
β€”
1.32
β€”
ns
tHL
Latch Hold Time
1.17
β€”
1.17
β€”
1.17
β€”
1.17
β€”
ns
tGOi
Latch Gate to Output/Feedback
MUX Time
β€”
0.33
β€”
0.33
β€”
0.33
β€”
0.33
ns




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