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LCMXO256LUTSE-3MN100I Datasheet(PDF) 2 Page - Lattice Semiconductor |
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LCMXO256LUTSE-3MN100I Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 95 page August 2006 Data Sheet DS1002 © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1002 Introduction_01.3 Features ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of non-volatile memory ■ Sleep Mode • Allows up to 100x static current reduction ■ TransFR™ Reconfiguration (TFR) • In-field logic update while system operates ■ High I/O to Logic Density • 256 to 2280 LUT4s • 73 to 271 I/Os with extensive package options • Density migration supported • Lead free/RoHS compliant packaging ■ Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.5 Kbits distributed RAM • Dedicated FIFO control logic ■ Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − PCI − LVDS, Bus-LVDS, LVPECL, RSDS ■ sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting ■ System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming Introduction The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfac- ing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. Table 1-1. MachXO Family Selection Guide Device LCMXO256 LCMXO640 LCMXO1200 LCMXO2280 LUTs 256 640 1200 2280 Dist. RAM (Kbits) 2.0 6.0 6.25 7.5 EBR SRAM (Kbits) 0 0 9.2 27.6 Number of EBR SRAM Blocks (9 Kbits) 0013 VCC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V Number of PLLs 0012 Max. I/O 78 159 211 271 Packages 100-pin TQFP (14x14 mm) 78 74 73 73 144-pin TQFP (20x20 mm) 113 113 113 100-ball csBGA (8x8 mm) 78 74 132-ball csBGA (8x8 mm) 101 101 101 256-ball ftBGA (17x17 mm) 159 211 211 324-ball ftBGA (19x19 mm) 271 MachXO Family Data Sheet Introduction |
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