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LC5512MC-75F256C Datasheet(PDF) 16 Page - Lattice Semiconductor

Part # LC5512MC-75F256C
Description  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC5512MC-75F256C Datasheet(HTML) 16 Page - Lattice Semiconductor

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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
16
Figure 15. PLL Block Diagram
Figure 16. Connection of Optional PLL Inputs and Outputs
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to Lattice technical note number TN1003, Lattice sysCLOCK PLL Usage
Guidelines.
SEC_OUT
CLK_OUT
PLL_LOCK
CLK_IN
PLL_RST
PLL_FBK
Input Clock
(M) Divider
Post-scalar
(V) Divider
VCO
and
Phase
Detector
Programable
Delay
Secondary
Clock
(K) Divider
Feedback
Loop
(N) Divider
Clock Net
Clock Net
PLL_LOCK
To GRP
CLK_OUT
From Macrocell
To GRP
To GRP
PLL_RST
From Macrocell
To GRP
PLL_FBK
From Macrocell
I/O Pin*
I/O Pin*
I/O Pin*
*See pinout table for details


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