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LC5512MC-75F672C Datasheet(PDF) 49 Page - Lattice Semiconductor |
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LC5512MC-75F672C Datasheet(HTML) 49 Page - Lattice Semiconductor |
49 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 49 Signal Descriptions Signal Names Descriptions TMS Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine. TCK Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state machine. TDI Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data. TDO Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out. TOE Input – Test Output Enable pin. TOE tristates all I/O pins when driven low. GOE0, GOE1 Input – Global output enable inputs. RESET Input – This pin resets all the registers in the device. The global polarity for this pin is selectable on a global basis. The default is active low. An external pull-down is required when polarity is set to active high. yzz Input/Output – These are the general purpose I/O used by the logic array. y is the MFB reference (alpha) and z is the macrocell reference (numeric) y: A-X (768 macrocells) y: A-P (512 macrocells) y: A-H (256 macrocells) z: 0-31 GND GND – Ground NC No connect VCC VCC – The power supply pins for core logic. VCCO0, VCCO1, VCCO2, VCCO3 VCC – The power supply pins for I/O banks 0, 1, 2, and 3. VREF0, VREF1, VREF2, VREF3 Input – This pin defines the reference voltage for I/O banks 0, 1, 2, and 3. GCLK0, GCLK1, GCLK2, GCLK3 Input – Global clock/clock enable inputs (see Figure 14 for differential pairing). CLK_OUT0, CLK_OUT1 Output – Optional clock output from PLL 0 and 1. PLL_RST0, PLL_RST1 Input – Optional input resets the M divider in PLL 0 and 1. PLL_FBK0, PLL_FBK1 Input – Optional feedback input for PLL 0 and 1. GNDP GND – Ground for PLLs. VCCP VCC – The power supply pin for PLLs. VCCJ VCC – The power supply for the IEEE 1149.1 interface. DATA x I/O – sysCONFIG data pins, bit x. CSB Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface. CFG0 Input – Defines SRAM configuration mode. Low: sysCONFIG port, high: E 2CMOS or IEEE 1149.1 TAP. PROGRAMB Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low to reload SRAM from E 2 memory. CCLK 1 Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of the clock. READ 1 Input – Drive high to perform reads from the sysCONFIG interface. INITB I/O – Indicates status of configuration. Can be driven low to inhibit configuration. DONE Output (open drain) – Indicates status of configuration. 1. These inputs should not toggle during power up for proper power-up configuration. |
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