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V826664K24S Datasheet(PDF) 5 Page - Mosel Vitelic, Corp

Part No. V826664K24S
Description  2.5 VOLT 64M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE
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Manufacturer  MOSEL [Mosel Vitelic, Corp]
Direct Link  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V826664K24S Datasheet(HTML) 5 Page - Mosel Vitelic, Corp

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MOSEL VITELIC
V826664K24S
5
V826664K24S Rev. 1.0 April 2002
Serial Presence Detect Information
Bin Sort:
B1 (PC266A @ CL = 2)
B0 (PC266B @ CL = 2.5)
A1 (PC200 @ CL = 2)
Byte #
Function described
Function Supported
Hex value
A1
B0
B1
A1
B0
B1
0
Defines # of Bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
10
0Ah
5
# of module Rows on this assembly
2 Bank
02h
6
Data width of this assembly
64 bits
40h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
8ns
7.5ns
7ns
80h
75h
70h
10
DDR SDRAM Access time from clock at CL=2.5
±0.8ns ±0.75ns ±0.75ns
80h
75h
75h
11
DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
00h
12
Refresh rate & type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
N/A
00h
15
Minimum clock delay for back-to-back random column
address
tCCD=1CLK
01h
16
DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Differential clock /
non Registered
20h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at CL =2
10ns
10ns
7.5ns
A0h
A0h
75h
24
DDR SDRAM Access time from clock at CL =2
±0.8ns ±0.75ns ±0.75ns
80h
75h
75h
25
DDR SDRAM cycle time at CL =1.5
-
-
-
00h
26
DDR SDRAM Access time from clock at CL =1.5
-
-
-
00h
27
Minimum row precharge time (=tRP)
20ns
20ns
20ns
50h
50h
50h
28
Minimum row activate to row active delay(=tRRD)
15ns
15ns
15ns
3Ch
3Ch
3Ch


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