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MC13224VR2 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MC13224VR2 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 48 page MC13224V Product Preview, Rev. 1.7 Freescale Semiconductor 5 — Advanced encryption/decryption hardware engine (AES 128-bit) • Supports standard IEEE 802.15.4 signaling with 250 kbps data rate • 32-bit ARM7TDMI-S CPU core with programmable performance up to 26 MHz (24 MHz typical) • Extensive on-board memory resources — 128 Kbyte serial FLASH memory (will be mirrored into RAM) — 96 Kbyte SRAM — 80 Kbyte ROM • Best-in-class power dissipation — 21mA typical RX current draw (DCD mode) with radio and MCU active — 28 mA typical TX current draw with radio and MCU active (coin cell capable) — 5mA maximum current draw with MCU active (radio off) — 0.9mA maximum current with MCU idle (radio off) — 1.1 μA maximum Hibernate current (retain 8 Kbyte SRAM contents) — 0.3 μA maximum Off current (device in reset) • Extensive sleep mode control and variation — Hibernate and Doze low power modes — Programmable degree of power down — Clock management — Onboard 2kHz oscillator for wake-up timer. — Optional 32.768 kHz crystal oscillator for accurate real-time sleep mode timing and wake-up with a possible sleep period greater than 36.4 hours — Wake-up through programmable timer, external real-time interrupts, or ADC timer • Extensive MCU peripherals set — Dedicated 802.15.4 modem/radio interface module (RIF) — Dedicated NVM SPI interface for managing FLASH memory — Two dedicated UART modules capable of 2Mbps with CTS/RTS support — SPI port with programmable master and slave operation — 8-pin keyboard interface (KBI) supports up to a 4x4 matrix. Also, provides up to 4 asynchronous interrupt inputs for wake-up — Two 12-bit analog-to-digital converters (ADCs) share 8 input channels — Four independent 16-bit timers with PWM capability. These can cascade in combinations up to 64-bit operation — Inter-integrated circuit (I2C) interface — Synchronous Serial Interface (SSI) with I2S and SPI capability and FIFO data buffering — Up to 64 programmable I/O shared by peripherals and GPIO • Powerful In-circuit debug and FLASH programming available via on-chip debug ports — JTAG debug port — Nexus extended feature debug port |
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Similar Description - MC13224VR2 |
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