Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.NET

X  

Preview PDF Download HTML

V827432K24S Datasheet(PDF) 6 Page - Mosel Vitelic, Corp

Part No. V827432K24S
Description  2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE
Download  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MOSEL [Mosel Vitelic, Corp]
Direct Link  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V827432K24S Datasheet(HTML) 6 Page - Mosel Vitelic, Corp

Back Button V827432K24S Datasheet HTML 2Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 3Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 4Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 5Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 6Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 7Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 8Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 9Page - Mosel Vitelic, Corp V827432K24S Datasheet HTML 10Page - Mosel Vitelic, Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 14 page
background image
6
MOSEL VITELIC
V827432K24S
V827432K24S Rev. 1.2 September 2002
28
Minimum row activate to row active delay(=tRRD)
15ns
15ns
15ns
12ns
3Ch
3Ch
3Ch
30h
29
Minimum RAS to CAS delay(=tRCD)
20ns
20ns
20ns
18ns
50h
50h
50h
48h
30
Minimum active to precharge time(=tRAS)
50ns
45ns
45ns
42ns
32h
2Dh
2Dh
2Ah
31
Module ROW density
256MB
40h
32
Command and address signal input setup time
1.1ns
0.9ns
0.9ns 0.75ns
B0h
90h
90h
75h
33
Command and address signal input hold time
1.1ns
0.9ns
0.9ns 0.75ns
B0h
90h
90h
75h
34
Data signal input setup time
0.6ns
0.5ns
0.5ns 0.45ns
60h
50h
50h
45h
35
Data signal input hold time
0.6ns
0.5ns
0.5ns 0.45ns
60h
50h
50h
45h
36-40
Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns
65ns
65ns
60ns
46h
41h
41h
3Ch
42
SDRAM device minimum active to autorefresh to active/auto-re-
fresh time (=tRFC)
80ns
75ns
75ns
72ns
50h
4Bh
4Bh
48h
43
SDRAM device maximum device cycle time (=tCK MAX)
12ns
12ns
12ns
12ns
30h
30h
30h
30h
44
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.6ns
0.5ns
0.5ns 0.45ns
3Ch
32h
32h
2Dh
45
SDRAM device maximum read datahold skew factor (=tQHS)
1ns
0.75ns 0.75ns 0.60ns
A0h
75h
75h
60h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
63
Checksum for Bytes 0 ~ 62
-
F9h
34h
04h
5Dh
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71
....... Manufacturer JEDEC ID code
00h
72
Manufacturing location
02=Taiwan 05=China 0A=S-CH
73-90
Module part number (ASCII)
V827432K24S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
95~98
Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~25
5
Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
A1
B0
B1
C0
A1
B0
B1
C0
Serial Presence Detect Information (cont.)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn