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HD74LV273AFPEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74LV273AFPEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 10 page Rev.3.00 Jun. 25, 2004 page 1 of 9 HD74LV273A Octal D-type Flip-Flops with Clear REJ03D0330–0300Z (Previous ADE-205-273A (Z)) Rev.3.00 Jun. 25, 2004 Description The HD74LV273A has eight edges trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery- powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • V CC = 2.0 V to 5.5 V operation • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V O (Max.) = 5.5 V (@VCC = 0 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±6 mA (@V CC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV273AFPEL SOP–20 pin (JEITA) FP–20DAV FP EL (2,000 pcs/reel) HD74LV273ARPEL SOP–20 pin (JEDEC) FP–20DBV RP EL (1,000 pcs/reel) HD74LV273ATELL TSSOP–20 pin TTP–20DAV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs CLR CLK D Output Q LX X L H ↑ HH H ↑ LL H ↓ XQ0 Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition Q0: Output level before the indicated steady state input conditions were established. |
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