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HD74LS642FPEL Datasheet(PDF) 4 Page - Renesas Technology Corp |
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HD74LS642FPEL Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 7 page HD74LS642 Rev.2.00, Feb.18.2005, page 4 of 6 Testing Method Test Circuit 1A 1B DIR G Input P.G. Zout = 50 Ω 4.5V S1 Output VCC RL CL Notes: 1. 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, are identical to abobe load circuit. 2. CL includes prove and jig capacitance. 3. S1 is a input-output switch. Waveforms 1 Input A (or B) Output B (or A) 3 V 0 V VOL VOH 1.3 V 1.3 V 1.3 V 1.3 V 10 % 10 % 90 % 90 % tPLH tPHL tTLH tTHL Note: Input pulse: tTLH ≤ 15 ns, t THL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% |
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